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AX58200 Datasheet(PDF) 89 Page - ASIX Electronics Corporation

Part # AX58200
Description  EtherCAT Slave Controller SoC
PDF  180 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX58200 Datasheet(HTML) 89 Page - ASIX Electronics Corporation

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Copyright © 2019 ASIX Electronics Corporation. All rights reserved.
AX58200
EtherCAT Slave Controller SoC
High Speed USB 2.0 Device Controller (HSUSBD)
2.32.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains both the
AHB master interface and AHB slave interface. CPU programs the USB controller registers through the AHB
slave interface. For IN or OUT transfer, the USB device controller needs to write data to memory or read data
from memory through the AHB master interface. The USB device controller is complaint with USB 2.0
specification and it contains 12 configurable endpoints in addition to control endpoint. These endpoints could be
configured to BULK, INTERRUPT or ISO. The USB device controller has a built-in DMA to relieve the load of
CPU.
2.32.2 Features
⚫
USB Specification reversion 2.0 compliant
⚫
Supports 12 configurable endpoints in addition to Control Endpoint
⚫
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction
⚫
Three different operation modes of an in-endpoint - Auto Validation mode, Manual Validation mode,
Fly mode
⚫
Supports DMA operation
⚫
4092 Bytes Configurable RAM used as endpoint buffer
⚫
Supports Endpoint Maximum Packet Size up to 1024 bytes
USB 2.0 Host Controller (USBH)
2.33.1 Overview
This chip is equipped with a USB 2.0 HS/FS Host Controller (USBH) that supports Enhanced Host Controller
Interface (EHCI) and Open Host Controller Interface (OpenHCI, OHCI) Specification, a register-level
description of a host controller, to manage the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer between system
memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data transfer,
collecting status and activity of USB bus, providing power control and detecting over current of attached USB
devices.
2.33.2 Features
⚫
Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
⚫
Supports Enhanced Host Controller Interface (EHCI) Specification Revision 1.0
⚫
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
⚫
Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
⚫
Supports Control, Bulk, Interrupt, Isochronous and Split transfers.
⚫
Supports an integrated Root Hub.
⚫
Supports a port routing logic to route full/low speed device to OHCI controller.
⚫
Supports two USB host port shared with USB device (OTG function).
⚫
Supports port power control and port over current detection.
⚫
Supports DMA for real-time data transfer.



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