AX58200 datasheet(33/180 Pages) ASIX

33 / 180 page

AX58200

EtherCAT Slave Controller SoC

Cortex® -M4 processor features:

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A low gate count processor core, with low latency interrupt processing that has:

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A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference

Manual

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Banked Stack Pointer (SP)

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Hardware integer divide instructions, SDIV and UDIV

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Handler and Thread modes

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Thumb and Debug states

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Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low

interrupt latency

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Automatic processor state saving and restoration for low latency Interrupt Service Routine

(ISR) entry and exit

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Support for ARMv6 big-endian byte-invariant or little-endian accesses

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Support for ARMv6 unaligned accesses

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Floating Point Unit (FPU) in the Cortex® -M4F processor providing:

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32-bit instructions for single-precision (C float) data-processing operations

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Combined Multiply and Accumulate instructions for increased precision (Fused MAC)

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Hardware support for conversion, addition, subtraction, multiplication with optional

accumulate, division, and square-root

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Hardware support for denormals and all IEEE rounding modes

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32 dedicated 32-bit single precision registers, also addressable as 16 double-word registers

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Decoupled three stage pipeline

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Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve

low latency interrupt processing. Features include:

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External interrupts. Configurable from 1 to 240 (the AX58200 configured with 64 interrupts)

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Bits of priority, configurable from 3 to 8

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Dynamic reprioritization of interrupts

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Priority grouping which enables selection of preempting interrupt levels and nonpreempting

interrupt levels

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Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt

processing without the overhead of state saving and restoration between interrupts.

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Processor state automatically saved on interrupt entry, and restored on interrupt exit with on

instruction overhead

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Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode

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Memory Protection Unit (MPU). An optional MPU for memory protection, including:

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Eight memory regions

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Sub Region Disable (SRD), enabling efficient use of memory regions

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The ability to enable a background region that implements the default memory map

attributes

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Low-cost debug solution that features:

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Debug access to all memory and registers in the system, including access to memory

mapped devices, access to internal core registers when the core is halted, and access to

AX58200 Datasheet(PDF) 33 Page - ASIX Electronics Corporation

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