AX58200 datasheet(64/180 Pages) ASIX

64 / 180 page

AX58200

EtherCAT Slave Controller SoC

General Purpose I/O (GPIO)

2.6.1

Overview

This chip has up to 56 General Purpose I/O pins to be shared with other function pins depending on the chip

configuration. These 56 pins are arranged in 6 ports named as PA, PB, PC, PE, PF and PH. Each of the 56 pins is

independent and has the corresponding register bits to control the pin mode function and data.

The EtherCAT slave controller (ESC) sub-system has up to 20 General Purpose I/O pins (names as IO[x]) to be

shared with other function pins depending on the chip configuration.

The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output, Open-

drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are depending on

CIOINI (CONFIG0[10]).

2.6.2

Features

⚫

Four I/O modes:

–

Quasi-bidirectional mode

–

Push-Pull Output mode

–

Open-Drain Output mode

–

Input only with high impendence mode

⚫

TTL/Schmitt trigger input selectable

⚫

I/O pin can be configured as interrupt source with edge/level setting

⚫

Supports High Drive and High Slew Rate I/O mode

⚫

Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting

–

CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset

–

CIOINI = 1, all GPIO pins in input mode after chip reset

⚫

I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode

⚫

Enabling the pin interrupt function will also enable the wake-up function

AX58200 Datasheet(PDF) 64 Page - ASIX Electronics Corporation