AX58200 datasheet(60/180 Pages) ASIX

60 / 180 page

AX58200

EtherCAT Slave Controller SoC

2.3.4

Peripherals Clock

Each peripheral clock has its own clock source selection. Refer to the CLK_CLKSEL1, CLK_CLKSEL2 and

CLK_CLKSEL3 register.

2.3.5

Power-down Mode Clock

When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are disabled.

Some clock sources and peripherals clock are still active in Power-down mode.

For theses clocks, which still keep active, are listed below:

⚫

Clock Generator

–

10 KHz internal low speed RC oscillator (LIRC) clock

–

32.768 KHz external low speed crystal oscillator (LXT) clock

⚫

Peripherals Clock (When the modules adopt LXT or LIRC as clock source)

2.3.6

Clock Output

This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divide-by-2 shift

registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function

pin. Therefore, there are 16 options of power-of-2 divided clocks with the frequency from Fin/21 to Fin/216 where

Fin is input clock frequency to the clock divider.

The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider output

frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).

When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to

CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and

stays in low state.

0000

0001

1110

1111

16 to 1

MUX

1/2

…...

FREQSEL

(CLK_CLKOCTL[3:0])

CLKO

16 chained

divide-by-2 counter

CLKOEN

(CLK_CLKOCTL[4])

Enable

divide-by-2 counter

DIV1EN

(CLK_CLKOCTL[5])

CLK1HZEN

(CLK_CLKOCTL[6])

1 Hz clock from RTC

LXT

LIRC

RTCSEL(CLK_CLKSEL3[8])

/32768

HCLK

LXT

HXT

HIRC

CLKOSEL (CLK_CLKSEL1[29:28])

Figure 2.3-6: Clock Output Block Diagram

AX58200 Datasheet(PDF) 60 Page - ASIX Electronics Corporation

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