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AX58200 Datasheet(PDF) 69 Page - ASIX Electronics Corporation |
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AX58200 Datasheet(HTML) 69 Page - ASIX Electronics Corporation |
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69 / 180 page ![]() 69 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC EPWM Generator and Capture Timer (EPWM) 2.12.1 Overview The chip provides two EPWM generators - EPWM0 and EPWM1. Each EPWM supports 6 channels of EPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit EPWM counter with 16- bit comparator. The EPWM counter supports up, down and up-down counter types. EPWM uses comparator compared with counter to generate events. These events use to generate EPWM pulse, interrupt and trigger signal for EADC/DAC to start conversion. The EPWM generator supports two standard EPWM output modes: Independent mode and Complementary mode, they have difference architecture. There are two output functions based on standard output modes: Group function and Synchronous function. Group function can be enabled under Independent mode or complementary mode. Synchronous function only enabled under complementary mode. Complementary mode has two comparators to generate various EPWM pulse with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for EADC. For EPWM output control unit, it supports polarity output, independent pin mask and brake functions. The EPWM generator also supports input capture function. It supports latch EPWM counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened. Capture function also supports PDMA to transfer captured data to memory. 2.12.2 Features 2.12.2.1 EPWM Function Features ⚫ Supports maximum clock frequency up to maximum PLL frequency ⚫ Supports up to two EPWM modules, each module provides 6 output channels ⚫ Supports independent mode for EPWM output/Capture input channel ⚫ Supports complementary mode for 3 complementary paired EPWM output channel – Dead-time insertion with 12-bit resolution – Synchronous function for phase control – Two compared values during one period ⚫ Supports 12-bit prescaler from 1 to 4096 ⚫ Supports 16-bit resolution EPWM counter – Up, down and up/down counter operation type ⚫ Supports one-shot or auto-reload counter operation mode ⚫ Supports group function ⚫ Supports synchronous function ⚫ Supports mask function and tri-state enable for each EPWM pin ⚫ Supports brake function – Brake source from pin, analog comparator and system safety events (clock failed, SRAM parity error, Brown-out detection and CPU lockup). – Noise filter for brake source from pin – Leading edge blanking (LEB) function for brake source from analog comparator – Edge detect brake source to control brake state until brake interrupt cleared – Level detect brake source to auto recover function after brake condition removed ⚫ Supports interrupt on the following events: |
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