DRV8426PWPR datasheet(25/49 Pages) TI1

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DRV8426

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SLOSE55 – MAY 2020

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7.3.8 Linear Voltage Regulators

A linear voltage regulator is integrated in the DRV8426 device. The DVDD regulator can be used to provide a

reference voltage. DVDD can supply a maximum of 2mA load. For proper operation, bypass the DVDD pin to

GND using a ceramic capacitor.

The DVDD output is nominally 5-V. When the DVDD LDO current load exceeds 2mA, the output voltage drops

significantly.

Figure 16. Linear Voltage Regulator Block Diagram

If a digital input must be tied permanently high (that is, Mx, DECAYx or TOFF), tying the input to the DVDD pin

instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in sleep

mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For

reference, logic level inputs have a typical pulldown of 200 k

Ω.

The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.

7.3.9 Logic Level, tri-level and quad-level Pin Diagrams

Figure 17 shows the input structure for M0, DECAY0, DECAY1 and ENABLE pins.

Figure 17. Tri-Level Input Pin Diagram

Figure 17 shows the input structure for M1 and TOFF pins.

DRV8426PWPR Datasheet(PDF) 25 Page - Texas Instruments