DRV8426PWPR datasheet(28/49 Pages) TI1

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DRV8426

SLOSE55 – MAY 2020

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Table 11. Fault Condition Summary (continued)

FAULT

CONDITION

CONFIGU

RATION

ERROR

REPORT

H-BRIDGE

CHARGE

PUMP

INDEXER

LOGIC

RECOVERY

Thermal Shutdown

(OTSD)

TJ > TTSD

ENABLE =

Hi-Z

nFAULT

Disabled

Operating

Latched

ENABLE =

nFAULT

Disabled

Operating

Automatic: TJ <

TOTSD - THYS_OTSD

7.4 Device Functional Modes

7.4.1 Sleep Mode (nSLEEP = 0)

The DRV8426 device state is managed by the nSLEEP pin. When the nSLEEP pin is low, the DRV8426 device

enters a low-power sleep mode. In sleep mode, all the internal MOSFETs are disabled and the charge pump is

disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep

mode. The DRV8426 device is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE

time must elapse before the device is ready for inputs.

7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)

The ENABLE pin is used to enable or disable the DRV8426 device. When the ENABLE pin is low, the output

drivers are disabled in the Hi-Z state.

7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)

When the nSLEEP pin is high, the ENABLE pin is Hi-Z or 1, and VM > UVLO, the device enters the active mode.

The tWAKE time must elapse before the device is ready for inputs.

7.4.4 nSLEEP Reset Pulse

A latched fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 20 µs and

shorter than 40 µs. If nSLEEP is low for longer than 40 µs but less than 120 µs, the faults are cleared and the

device may or may not shutdown, as shown in the timing diagram (see Figure 21). This reset pulse does not

affect the status of the charge pump or other functional blocks.

Figure 21. nSLEEP Reset Pulse

Table 12 lists a summary of the functional modes.

Table 12. Functional Modes Summary

CONDITION

CONFIGURA

TION

H-BRIDGE

DVDD

Regulator

CHARGE PUMP

INDEXER

Logic

Sleep mode

4.5 V < VM < 33 V

nSLEEP pin

= 0

Disabled

Operating

4.5 V < VM < 33 V

nSLEEP pin

= 1

ENABLE pin

= 1 or Hi-Z

Operating

DRV8426PWPR Datasheet(PDF) 28 Page - Texas Instruments

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