DRV8426PWPR datasheet(27/49 Pages) TI1

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DRV8426

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SLOSE55 – MAY 2020

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7.3.10.2 CP Undervoltage Lockout (CPUV)

If at any time the voltage on the CP pin falls below the CPUV voltage, all the outputs are disabled, and the

nFAULT pin is driven low. The charge pump remains active during this condition. Normal operation resumes

(motor-driver operation and nFAULT released) when the CP undervoltage condition is removed.

7.3.10.3 Overcurrent Protection (OCP)

An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this

current limit persists for longer than the tOCP time, the FETs in both H-bridges are disabled and the nFAULT pin

is driven low. The charge pump remains active during this condition. The overcurrent protection can operate in

two different modes: latched shutdown and automatic retry.

7.3.10.3.1

Latched Shutdown

The ENABLE pin of the DRV8426 has to be made Hi-Z to select latched shutdown mode. In this mode, after an

OCP event, the outputs are disabled and the nFAULT pin is driven low. Once the OCP condition is removed,

normal operation resumes after applying an nSLEEP reset pulse or a power cycling.

7.3.10.3.2

Automatic Retry

The ENABLE pin of the DRV8426 has to be connected to DVDD to select automatic retry mode. In this mode,

after an OCP event the outputs are disabled and the nFAULT pin is driven low. Normal operation resumes

automatically (motor-driver operation and nFAULT released) after the tRETRY time has elapsed and the fault

condition is removed.

Errata: For the prototype samples, the driver output pins (AOUT1, AOUT2, BOUT1, BOUT2) are pulled high to

VVM when the device enter low-power sleep mode until VCP discharges below VCPUV. This behavior will be

corrected in the production device release in which the output pins will immediately enter high-impedance state

(Hi-Z) when the device enters sleep mode.

7.3.10.4 Thermal Shutdown (OTSD)

If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled, and

the nFAULT pin is driven low. The charge pump is disabled during this condition. The thermal shutdown

protection can operate in two different modes: latched shutdown and automatic retry.

7.3.10.4.1

Latched Shutdown

The ENABLE pin of the DRV8426 has to be made Hi-Z to select latched shutdown mode. In this mode, after an

OTSD event, the relevant outputs are disabled and the nFAULT pin is driven low. After the junction temperature

falls below the overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD), normal operation

resumes after applying an nSLEEP reset pulse or a power cycling.

7.3.10.4.2

Automatic Retry

The ENABLE pin of the DRV8426 has to be connected to DVDD to select automatic retry mode. In this mode,

after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. Normal operation resumes

(motor-driver operation and the nFAULT line released) when the junction temperature falls below the

overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD).

Table 11. Fault Condition Summary

FAULT

CONDITION

CONFIGU

RATION

ERROR

REPORT

H-BRIDGE

CHARGE

PUMP

INDEXER

LOGIC

RECOVERY

VM undervoltage

(UVLO)

VM < VUVLO

—

nFAULT

Disabled

Reset

(VDVDD <

3.9 V)

Automatic: VM >

VUVLO

CP undervoltage

(CPUV)

CP < VCPUV

—

nFAULT

Disabled

Operating

VCP > VCPUV

Overcurrent (OCP)

IOUT > IOCP

ENABLE =

Hi-Z

nFAULT

Disabled

Operating

Latched

ENABLE =

nFAULT

Disabled

Operating

Automatic retry:

tRETRY

DRV8426PWPR Datasheet(PDF) 27 Page - Texas Instruments

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