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DRV8426PWPR Datasheet(PDF) 26 Page - Texas Instruments |
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DRV8426PWPR Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 49 page ![]() Output nFAULT 26 DRV8426 SLOSE55 – MAY 2020 www.ti.com Product Folder Links: DRV8426 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Figure 18. Quad-Level Input Pin Diagram Figure 19 shows the input structure for STEP, DIR and nSLEEP pins. Figure 19. Logic-Level Input Pin Diagram 7.3.9.1 nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is detected, the nFAULT pin will be logic low. nFAULT pin will be high after power-up. For a 5-V pullup, the nFAULT pin can be tied to the DVDD pin with a resistor. For a 3.3-V pullup, an external 3.3-V supply must be used. Figure 20. nFAULT Pin 7.3.10 Protection Circuits The DRV8426 device is fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, and device overtemperature events. 7.3.10.1 VM Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the UVLO-threshold voltage for the voltage supply, all the outputs are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this condition. Normal operation resumes (motor-driver operation and nFAULT released) when the VM undervoltage condition is removed. |
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