DSPIC33EP128GS708 datasheet(267/484 Pages) MICROCHIP

267 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 267

dsPIC33EPXXXGS70X/80X FAMILY

bit 2-0

MODE<2:0>: CLCx Mode bits

111 = Single Input Transparent Latch with S and R

110 = JK Flip-Flop with R

101 = Two-Input D Flip-Flop with R

100 = Single Input D Flip-Flop with S and R

011 = SR Latch

010 = Four-Input AND

001 = Four-Input OR-XOR

000 = Four-Input AND-OR

CLCxCONL: CLCx CONTROL REGISTER (LOW) (CONTINUED)

CLCxCONH: CLCx CONTROL REGISTER (HIGH)

U-0

—

bit 15

bit 8

U-0

R/W-0

—

G4POL

G3POL

G2POL

G1POL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-4

Unimplemented: Read as ‘0’

bit 3

G4POL: Gate 4 Polarity Control bit

1 = Channel 4 logic output is inverted when applied to the logic cell

0 = Channel 4 logic output is not inverted

bit 2

G3POL: Gate 3 Polarity Control bit

1 = Channel 3 logic output is inverted when applied to the logic cell

0 = Channel 3 logic output is not inverted

bit 1

G2POL: Gate 2 Polarity Control bit

1 = Channel 2 logic output is inverted when applied to the logic cell

0 = Channel 2 logic output is not inverted

bit 0

G1POL: Gate 1 Polarity Control bit

1 = Channel 1 logic output is inverted when applied to the logic cell

0 = Channel 1 logic output is not inverted

DSPIC33EP128GS708 Datasheet(PDF) 267 Page - Microchip Technology

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