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DSPIC33EP128GS708 Datasheet(PDF) 273 Page - Microchip Technology

Part # DSPIC33EP128GS708
Description  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33EP128GS708 Datasheet(HTML) 273 Page - Microchip Technology

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 2016-2018 Microchip Technology Inc.
DS70005258C-page 273
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 21-4:
CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
G2D4T: Gate 2 Data Source 4 True Enable bit
1 = Data Source 4 non-inverted signal is enabled for Gate 2
0 = Data Source 4 non-inverted signal is disabled for Gate 2
bit 14
G2D4N: Gate 2 Data Source 4 Negated Enable bit
1 = Data Source 4 inverted signal is enabled for Gate 2
0 = Data Source 4 inverted signal is disabled for Gate 2
bit 13
G2D3T: Gate 2 Data Source 3 True Enable bit
1 = Data Source 3 non-inverted signal is enabled for Gate 2
0 = Data Source 3 non-inverted signal is disabled for Gate 2
bit 12
G2D3N: Gate 2 Data Source 3 Negated Enable bit
1 = Data Source 3 inverted signal is enabled for Gate 2
0 = Data Source 3 inverted signal is disabled for Gate 2
bit 11
G2D2T: Gate 2 Data Source 2 True Enable bit
1 = Data Source 2 non-inverted signal is enabled for Gate 2
0 = Data Source 2 non-inverted signal is disabled for Gate 2
bit 10
G2D2N: Gate 2 Data Source 2 Negated Enable bit
1 = Data Source 2 inverted signal is enabled for Gate 2
0 = Data Source 2 inverted signal is disabled for Gate 2
bit 9
G2D1T: Gate 2 Data Source 1 True Enable bit
1 = Data Source 1 non-inverted signal is enabled for Gate 2
0 = Data Source 1 non-inverted signal is disabled for Gate 2
bit 8
G2D1N: Gate 2 Data Source 1 Negated Enable bit
1 = Data Source 1 inverted signal is enabled for Gate 2
0 = Data Source 1 inverted signal is disabled for Gate 2
bit 7
G1D4T: Gate 1 Data Source 4 True Enable bit
1 = Data Source 4 non-inverted signal is enabled for Gate 1
0 = Data Source 4 non-inverted signal is disabled for Gate 1
bit 6
G1D4N: Gate 1 Data Source 4 Negated Enable bit
1 = Data Source 4 inverted signal is enabled for Gate 1
0 = Data Source 4 inverted signal is disabled for Gate 1
bit 5
G1D3T: Gate 1 Data Source 3 True Enable bit
1 = Data Source 3 non-inverted signal is enabled for Gate 1
0 = Data Source 3 non-inverted signal is disabled for Gate 1
bit 4
G1D3N: Gate 1 Data Source 3 Negated Enable bit
1 = Data Source 3 inverted signal is enabled for Gate 1
0 = Data Source 3 inverted signal is disabled for Gate 1



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