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DSPIC33EP128GS708 Datasheet(PDF) 277 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 277 Page - Microchip Technology |
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277 / 484 page ![]() 2016-2018 Microchip Technology Inc. DS70005258C-page 277 dsPIC33EPXXXGS70X/80X FAMILY 22.0 HIGH-SPEED, 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) dsPIC33EPXXXGS70X/80X devices have a high-speed, 12-bit Analog-to-Digital Converter (ADC) that features a low conversion latency, high resolution and over- sampling capabilities to improve performance in AC/DC, DC/DC power converters. 22.1 Features Overview The high-speed, 12-bit multiple SARs Analog-to-Digital Converter (ADC) includes the following features: • Five ADC Cores: Four Dedicated Cores and One Shared (common) Core • User-Configurable Resolution of up to 12 Bits for each Core • Up to 3.25 Msps Conversion Rate per Channel at 12-Bit Resolution • Low Latency Conversion • Up to 22 Analog Input Channels, with a Separate 16-Bit Conversion Result Register for each Input • Conversion Result can be Formatted as Unsigned or Signed Data, on a per Channel Basis, for All Channels • Single-Ended and Pseudodifferential Conversions are available on All ADC Cores • Simultaneous Sampling of up to Five Analog Inputs • Channel Scan Capability • Multiple Conversion Trigger Options for each Core, including: - PWM1 through PWM6 (primary and secondary triggers, and current-limit event trigger) - PWM Special Event Trigger - Timer1/Timer2 period match - Output Compare 1 and event trigger - External pin trigger event (ADTRG31) - Software trigger • Two Integrated Digital Comparators with Dedicated Interrupts: - Multiple comparison options - Assignable to specific analog inputs • Two Oversampling Filters with Dedicated Interrupts: - Provide increased resolution - Assignable to a specific analog input The module consists of five independent SAR ADC cores. Simplified block diagrams of the multiple SARs 12-bit ADC are shown in Figure 22-1, Figure 22-2 and Figure 22-3. The analog inputs (channels) are connected through multiplexers and switches to the Sample-and-Hold (S&H) circuit of each ADC core. The core uses the channel information (the output format, the Measure- ment mode and the input number) to process the analog sample. When conversion is complete, the result is stored in the result buffer for the specific analog input, and passed to the digital filter and digital comparator if they were configured to use data from this particular channel. The ADC module can sample up to five inputs at a time (four inputs from the dedicated SAR cores and one from the shared SAR core). If multiple ADC inputs request conversion on the shared core, the module will convert them in a sequential manner, starting with the lowest order input. The ADC provides each analog input the ability to specify its own trigger source. This capability allows the ADC to sample and convert analog inputs that are associated with PWM generators operating on independent time bases. Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGS70X/80X family of devices. It is not intended to be a compre- hensive reference source. To complement the information in this data sheet, refer to “12-Bit High-Speed, Multiple SARs A/D Converter (ADC)” (DS70005213) in the “dsPIC33/PIC24 Family Reference Man- ual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. |
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