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DSPIC33EP128GS708 Datasheet(PDF) 316 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 316 Page - Microchip Technology |
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316 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 316 2016-2018 Microchip Technology Inc. REGISTER 23-4: CxFCTRL: CANx FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS2 DMABS1 DMABS0 — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA4 FSA3 FSA2 FSA1 FSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in RAM 101 = 24 buffers in RAM 100 = 16 buffers in RAM 011 = 12 buffers in RAM 010 = 8 buffers in RAM 001 = 6 buffers in RAM 000 = 4 buffers in RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Receive Buffer RB31 11110 = Receive Buffer RB30 • • • 00001 = Transmit/Receive Buffer TRB1 00000 = Transmit/Receive Buffer TRB0 |
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