Z8F082ASH020SC datasheet(133/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Analog-to-Digital Converter

Z8 Encore! XP® F08xA Series

Product Specification

115

Also note that in the second term, the multiplication should be performed before the divi-

sion by 216. Otherwise, the second term will incorrectly evaluate to zero.

Although the ADC can be used without the gain and offset compensation, it does exhibit

non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC

range but requires the ADC results to be scaled by a factor of 8/7.

Input Buffer Stage

Many applications require the measurement of an input voltage source with a high output

impedance. This ADC provides a buffered input for such situations. The drawback of the

buffered input is a limitation of the input range. When using unity gain buffered mode, the

input signal must be prevented from coming within 300mV of VSS and 400mV of VDD.

Very small input voltages (less than 300mV) may not be measured in BUFFERED mode.

This condition applies only to the input voltage level (with respect to ground) of each dif-

ferential input signal. The actual differential input voltage magnitude may be less than 300

mV.

The 20x gain mode has more complicated input signal requirements. Similar to the unity

gain buffered mode, both inputs must be prevented from coming within 300mV of either

supply. Because of the limitations in the output swing of the 20x gain stage, the following

additional constraints apply:

430 mV < 10 (Vinp - Vinn) + Vcm < VDD - 430mV

430 mV < 10 (Vinn - Vinp) + Vcm < VDD - 430mV

where

Vcm = (Vinp - Vinn)/2 (common mode voltage),

Vinp is the positive ADC input voltage,

Vinn is the negative ADC input voltage

These differential mode limitations explain that the common mode voltage of the differen-

tial inputs must be significantly above ground and below the supply, and that the differen-

tial magnitude must exceed these limitations.

The input range of the unbuffered ADC swings from VSS to VDD. Input signals smaller

than 300mV must use the unbuffered input mode. If these signals do not contain low out-

put impedances, they might require off-chip buffering.

Signals outside the allowable input range can be used without instability or device dam-

age. Any ADC readings made outside the input range are subject to greater inaccuracy

than specified.

Caution:

Z8F082ASH020SC Datasheet(PDF) 133 Page - Zilog, Inc.