48SWTQFN-EP datasheet(59/103 Pages) MAXIM

59 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 59

Control Channel and Register Programming

The control channel is available for the µC to send and

receive control data over the serial link simultaneously

with the high-speed data. The µC controls the link from

either the serializer or the deserializer side to support

video-display or image-sensing applications. The control

channel between the µC and serializer or deserializer

runs in base mode or bypass mode according to the

mode-selection input (MS) of the device connected to

the µC. Base mode is a half-duplex control channel and

bypass mode is a full-duplex control channel. The total

maximum forward or reverse control-channel delay is 2µs

(UART) or 2-bit times (I2C) from the input of one device

to the output of the other. I2C delay is measured from a

START condition to a STOP condition.

UART Interface

In base mode, the µC is the host and can access the

registers of both the serializer and deserializer from either

side of the link using the GMSL UART protocol. The µC

can also program the peripherals on the remote side by

sending the UART packets to the serializer or deserializer,

with the UART packets converted to I2C by the device

on the remote side of the link. The µC communicates

with a UART peripheral in base mode (through INTTYPE

UART protocol of the serializer/deserializer. The device

addresses of the serializer and deserializer in base mode

are programmable.

When the peripheral interface is I2C, the serializer/

deserializer convert UART packets to I2C that have

device addresses different from those of the serializer or

deserializer. The converted I2C bit rate is the same as the

original UART bit rate.

The deserializer uses differential line coding to send signals

over the reverse channel to the serializer. The bit rate of the

control channel is 9.6kbps to 1Mbps in both directions. The

serializer and deserializer automatically detect the control-

channel bit rate in base mode. Packet bit-rate changes can

be made in steps of up to 3.5 times higher or lower than the

previous bit rate. See the Changing the Clock Frequency

section for more information.

Table 9. fSRC Settings

*MCLK is not divided when using WS as the MCLK source. MCLK divider must still be set to a nonzero number for MCLK to be

enabled.

Figure 40. Audio Channel Output Format

MCLKWS SETTING

(REGISTER 0x15, D1)

MCLKSRC SETTING

(REGISTER 0x12, D7)

DATA RATE

SETTING

BIT-WIDTH SETTING

MCLK SOURCE

FREQUENCY (fSRC)

High speed

(DRS = 0)

24-bit or high-bandwidth mode

3 x fPIXEL

32-bit mode

4 x fPIXEL

Low speed

(DRS = 1)

24-bit or high-bandwidth mode

6 x fPIXEL

32-bit mode

8 x fPIXEL

—

Internal oscillator

(120MHz typ)

—

WS*

I2S

TDM 256

SCK

8 TO 32 BITS

256 BITS

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