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48SWTQFN-EP Datasheet(PDF) 48 Page - Maxim Integrated Products |
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48SWTQFN-EP Datasheet(HTML) 48 Page - Maxim Integrated Products |
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48 / 103 page ![]() MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 48 Auto Pixel-Per-Line Feature For proper operation, the device requires the information of number of pixels in DE high period. Program the pixel count into registers 0x61 and 0x62. Alternatively, the device can automatically count the number of pixels in DE high period. Setting the AUTOPPL bit high enables this function. In this mode, the device counts the number of pixels in every DE high period and compares the result with the number of pixels in the previous DE high period. If both numbers are within ±4 pixels of each other, the deserializer accepts this count as valid count and uses the number to pack- etize the video data. An AUTOPPL error is issued only when the current pixel count does not match the previous pixel count. An invalid count (±5 or more pixels) stops the packet transmission and issues an AUTOPPL error. This allows the device to tolerate some noise while alerting the user of an error. Table 2 Video Output Map (RGB and YUV) 1. Refer to the GMSL serializer data sheet for details. 2. YUV defaults to muxed input mode (Cb, Y0, Cr, Y1). Set INPUTBW = 1 to use normal input mode (CBY0, CrY1). 3. Data type available when BWS = high or open, only. *VESA/oLDI bits are mapped to MIPI according to OLDI bit (D4 or register 0x60). Set oLDI bit low when using VESA input or high when using an oLDI input. oLDI defines bits [5:0] as MSB and bits [6:7] as LSB. **12-bit YUV422 sent using CSI-2 user-defined data type (0x30). The output byte sequence is CB[11:4], Y0[11:4], [CB[3:0], Y0[3:0]], CR[11:4], Y1[11:4], [CR[3:0], and Y1[3:0]]. GMSL INPUT BITS1 RGB YUV4222 666 565 8883* 8-BIT MUXED 10-BIT MUXED 8-BIT 10-BIT3 12-BIT3** DIN0 R0 R0 R0 Y/Cb/Cr0 Y/Cb/Cr0 Cb/Cr0 Cb/Cr0 Cb/Cr0 DIN1 R1 R1 R1 Y/Cb/Cr1 Y/Cb/Cr1 Cb/Cr1 Cb/Cr1 Cb/Cr1 DIN2 R2 R2 R2 Y/Cb/Cr2 Y/Cb/Cr2 Cb/Cr2 Cb/Cr2 Cb/Cr2 DIN3 R3 R3 R3 Y/Cb/Cr3 Y/Cb/Cr3 Cb/Cr3 Cb/Cr3 Cb/Cr3 DIN4 R4 R4 R4 Y/Cb/Cr4 Y/Cb/Cr4 Cb/Cr4 Cb/Cr4 Cb/Cr4 DIN5 R5 G0 R5 Y/Cb/Cr5 Y/Cb/Cr5 Cb/Cr5 Cb/Cr5 Cb/Cr5 DIN6 G0 G1 G0 Y/Cb/Cr6 Y/Cb/Cr6 Cb/Cr6 Cb/Cr6 Cb/Cr6 DIN7 G1 G2 G1 Y/Cb/Cr7 Y/Cb/Cr7 Cb/Cr7 Cb/Cr7 Cb/Cr7 DIN8 G2 G3 G2 — Y/Cb/Cr8 Y0 Cb/Cr8 Cb/Cr8 DIN9 G3 G4 G3 — Y/Cb/Cr9 Y1 Cb/Cr9 Cb/Cr9 DIN10 G4 G5 G4 — — Y2 Y0 Cb/Cr10 DIN11 G5 B0 G5 — — Y3 Y1 Cb/Cr11 DIN12 B0 B1 B0 — — Y4 Y2 Y0 DIN13 B1 B2 B1 — — Y5 Y3 Y1 DIN14 B2 B3 B2 — — Y6 Y4 Y2 DIN15 B3 B4 B3 — — Y7 Y5 Y3 DIN16 B4 — B4 — — — Y6 Y4 DIN17 B5 — B5 — — — Y7 Y5 DIN18 HS HS HS HS HS HS HS HS DIN19 VS VS VS VS VS VS VS VS DIN20 DE DE DE DE DE DE DE DE DIN21 — — R6 — — — Y8 Y6 DIN22 — — R7 — — — Y9 Y7 DIN23 — — G6 — — — — Y8 DIN24 — — G7 — — — — Y9 DIN25 — — B6 — — — — Y10 DIN26 — — B7 — — — — Y11 |
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