48SWTQFN-EP datasheet(71/103 Pages) MAXIM

71 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 71

High-Immunity Reverse Control-Channel Mode

The deserializer contains a high-immunity reverse

control-channel mode, which has increased robustness at

half the bit rate over the standard GMSL reverse control-

channel link (Table 14). Set HIM on the serializer and

deserializer to use high-immunity mode at power-up. Set

the HIGHIMM bit high in both the serializer and dese-

rializer to enable high-immunity mode at any time after

power-up. Set the HIGHIMM bit low in both the serializer

and deserializer to use the legacy reverse control-channel

mode. The deserializer reverse channel mode is not avail-

able for 500µs/1.92ms after the reverse control-channel

mode is changed through the serializer/deserializer’s

HIGHIMM bit setting, respectively. The user must set HIM

or the HIGHIMM bits to the same value for proper reverse

control-channel communication.

In high-immunity mode, Set HPFTUNE = 00 in the equal-

izer, if the serial bit rate = [pixel clock x 30 (BWS = low

or open) or 40 (BWS = high)] is larger than 1Gbps when

BWS is low or high. When BWS = open, set HPFTUNE =

00 when the serial bit rate is larger than 2GBps.

By default, high-immunity mode uses a 500kbps bit rate.

Set REVFAST =1 (D7 in register 0x1A in the serializer and

1Mbps bit rate. Certain limitations apply when using the

fast high-immunity mode (Table 15).

Sleep Mode

The deserializers have sleep mode to reduce power

consumption. The devices enter or exit sleep mode by a

command from a remote µC using the control channel.

Set the SLEEP bit to 1 to initiate sleep mode. Entering

sleep mode resets the HDCP registers, but not the con-

figuration registers. The deserializer sleeps after serial

link inactivity or 8ms (whichever arrives first) after setting

its SLEEP = 1. See the Link Startup Procedure section

for details on waking up the device for different µC and

starting conditions.

To wake up from the local side, send an arbitrary control-

channel command to the deserializer, wait for 5ms for the

chip to power up, and then write 0 to SLEEP register bit

to make the wake-up permanent. To wake up from the

remote side, enable serialization. The deserializer detects

the activity on serial link and then when it locks, it auto-

matically sets its SLEEP register bit to 0.

Power-Down Mode

The deserializers have a power-down mode that further

reduces power consumption compared to sleep mode. Set

PWDN

low to enter power-down mode. In power-down, the

parallel outputs remain high impedance. Entering power-

down resets the device’s registers. Upon exiting power-

down, the state of external pins ADD0–ADD2, CX/TP,

I2CSEL, DRS, EQS, HIM/CNTL1, and BWS are latched.

Table 14. Reverse Control-Channel Modes

Table 15. Fast High-Immunity Mode Requirements

Fast high-immunity mode requires DRS = 0.

X = Don’t care.

HIGHIMM BIT OR

SD/HIM PIN SETTING

REVFAST

BIT

REVERSE CONTROL-CHANNEL MODE

MAX UART/

I2C BIT RATE

(kbps)

Low (0)

Legacy reverse control-channel mode (compatible with all GMSL

devices)

1000

High (1)

High-immunity mode

500

Fast high-immunity mode

1000

BWS SETTING

ALLOWED PIXEL CLOCK FREQUENCY (MHz)

Low

> 41.66

High

> 30

Open

> 83.33

48SWTQFN-EP Datasheet(PDF) 71 Page - Maxim Integrated Products

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