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48SWTQFN-EP Datasheet(PDF) 76 Page - Maxim Integrated Products |
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48SWTQFN-EP Datasheet(HTML) 76 Page - Maxim Integrated Products |
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76 / 103 page ![]() MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 76 Table 18. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled NO. µC HDCP GMSL SERIALIZER HDCP GMSL DESERIALIZER 1 — Generates Ri and updates the RI register every 128 VSYNC cycles. Generates Ri’ and updates the RI’ register every 128 VSYNC cycles. 2 — Continues to encrypt and transmit A/V data. Continues to receive, decrypt, and output A/V data. 3 Every 128 video frames (VSYNC cycles) or every 2s. — — 4 Reads RI from the GMSL serializer. — — 5 Reads RI’ from the deserializer. — — 6 Reads RI again from the GMSL serializer and makes sure it is stable (matches the previous RI that it has read from the GMSL serializer). If RI is not stable, go back to step 5. — — 7 If RI matches RI’, the link integrity check is successful; go back to step 3. — — 8 If RI does not match RI’, the link integrity check fails. After the detection of failure of link integrity check, the FC makes sure that A/V data not requiring protection (low-value content) is available at the GMSL serializer inputs (such as blue or informative screen). Alternatively, the FORCE_VIDEO and FORCE_AUDIO bits of the GMSL serializer can be used to mask A/V data input of the GMSL serializer. — — 9 Writes 0 to the ENCRYPTION_ENABLE bit of the GMSL serializer and deserializer. Disables encryption and transmits low-value content A/V data. Disables decryption and outputs low- value content A/V data. 10 Restarts authentication by writing 1 to the RESET_HDCP bit followed by writing 1 to the START_AUTHENTICATION bit in the GMSL serializer. — — |
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