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48SWTQFN-EP Datasheet(PDF) 18 Page - Maxim Integrated Products |
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48SWTQFN-EP Datasheet(HTML) 18 Page - Maxim Integrated Products |
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18 / 103 page ![]() MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 18 PIN NAME FUNCTION 1 INTOUT A/V Status Register Interrupt Output. Indicates new data in the A/V status registers. INTOUT is reset when the A/V status registers are read. 2 GPI General-Purpose Input with Internal Pulldown to EP. The serializer GPO (or INT) output follows GPI. 3 I2CSEL I2C Select. Control channel interface protocol select input with internal pulldown to EP. Set I2CSEL = high to select I2C interface. Set I2CSEL = low to select UART interface. 4 GPIO0 Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD 5 BWS Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set BWS = low, with 6kΩ (max) pulldown for 24-bit mode. Set BWS = high, with 6kΩ (max) pullup to IOVDD for 32-bit mode. Set BWS = open for high-bandwidth mode. 6, 47 AVDD3 3.3V Analog Power Supply. Bypass AVDD3 to EP with 0.1µF and 0.001µF capacitors as close as possible to the device with the smaller capacitor closest to AVDD3. 7 IN+ Noninverting Coax/Twisted-Pair Serial Input 8 IN- Inverting Coax/Twisted-Pair Serial Input TQFN/SWTQFN (7mm x 7mm x 0.75mm) CONNECT EP TO GROUND PLANE EP* MAX9288 MAX9290 TOP VIEW 13 14 15 16 17 18 19 20 21 22 23 24 RX/SDA + TX/SCL PWDN WS SCK SD ADD2/CNTL2 HIM/CNTL1 IOVDD CDS DVDD18 RSVD 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 CX/TP AVDD3 LMN1 LMN0 LFLT IOVDD DRS ERR LOCK ADD0/CNTL0 ADD1/CNTL3 DVDD18 36 35 34 33 32 31 30 29 28 27 26 25 Pin Description Pin Configuration |
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