48SWTQFN-EP datasheet(14/103 Pages) MAXIM

14 / 103 page

(VAVDD18 = VDVDD18 = 1.7V to 1.9V, VAVDD3 = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected

to PCB ground (GND), TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD18 = VDVDD18 = VIOVDD = 1.8V,

VAVDD3 = 3.3V, TA = +25°C.)

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

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PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Audio Skew Relative to Video

tASK

Video and audio synchronized

3 x

tWS

4 x tWS

µs

SCK, SD, WS Rise-and-Fall

Time

tR, tF

20% to 80%

CL = 10pF, DCS = 1

0.3

3.1

CL = 5pF, DCS = 0

0.4

3.8

SD, WS Valid Time Before SCK

(2-Channel I2S)

tDVB1

tSCK = 1/fSCK, Figure 12

0.20 x tSCK

0.5 x

tSCK

SD, WS Valid Time After SCK

(2-Channel I2S)

tDVA1

tSCK = 1/fSCK, Figure 12

0.20 x tSCK

0.5 x

tSCK

SD, WS Valid Time Before SCK

(8-Channel TDM)

tDVB2

tSCK = 1/fSCK, Figure 12

0.20 x tSCK

0.5 x

tSCK

SD, WS Valid Time After SCK

(8-Channel TDM)

tDVA2

tSCK = 1/fSCK, Figure 12

0.20 x tSCK

0.5 x

tSCK

HIGH-SPEED DIFFERENTAIL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10)

20% to 80% Rise Time and Fall

Time

tR, tF

Bit rate ≤ 1Gbps

0.3

100

Data-to-Clock Skew

tSKW

-0.15

+0.15

UI Instantaneous

UIINS

12.5

Common-Level Variation Above

450MHz

ΔVCM

mVRMS

Common-Level Variation

Between 50MHz to 450MHz

mVPEAK

LOW-SPEED DIFFERENTIAL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10)

15% to 85% Rise Time and Fall

Time

tRLP/tFLP

30% to 85% Rise Time and Fall

Time Transition from HS to LP

tREOP

GENERAL CSI-2 TIMING SPECIFICATIONS (Note 10, Figure 13)

Start of Transmission: Clock

Prepare Time

tCLK-

PREPARE

Time that the transmitter drives the clock

lane LP-00 line state immediately before

HS-0 line state starting the HS transition

End of Transmission: Clock

Trail Time

tCLK-TRAIL

Time that the transmitter drives the HS-0

state after the last payload clock bit of a

HS transmission burst

Clock Start of Transmission

Time

tCLK-

PREPARE

+ tCLK-

ZERO

tCLK-PREPARE + time that the transmitter

drives the HS-0 state prior to starting the

clock

300

AC Electrical Characteristics (continued)

48SWTQFN-EP Datasheet(PDF) 14 Page - Maxim Integrated Products

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