48SWTQFN-EP datasheet(63/103 Pages) MAXIM

63 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 63

START and STOP Conditions

Both SCL and SDA remain high when the interface is not

busy. A master signals the beginning of a transmission

with a START (S) condition by transitioning SDA from high

to low while SCL is high (see Figure 47). When the mas-

ter has finished communicating with the slave, it issues

a STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission.

Bit Transfer

One data bit is transferred during each clock pulse

(Figure 48). The data on SDA must remain stable while

SCL is high.

Acknowledge

The acknowledge bit is a clocked 9th bit that the recipient

uses to handshake receipt of each byte of data (Figure 49).

Thus, each byte transferred effectively requires 9 bits.

The master generates the 9th clock pulse, and the recipi-

ent pulls down SDA during the acknowledge clock pulse.

The SDA line is stable low during the high period of the

clock pulse. When the master is transmitting to the slave

device, the slave device generates the acknowledge bit

because the slave device is the recipient. When the slave

device is transmitting to the master, the master generates

the acknowledge bit because the master is the recipient.

The device generates an acknowledge even when the

forward control channel is not active. To prevent acknowl-

edge generation when the forward control channel is not

active, set the I2CLOCACK bit low.

Figure 47. START and STOP Conditions

Figure 48. Bit Transfer

SDA

SCL

START

CONDITION

STOP

CONDITION

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

48SWTQFN-EP Datasheet(PDF) 63 Page - Maxim Integrated Products

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