48SWTQFN-EP datasheet(65/103 Pages) MAXIM

65 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 65

Bus Reset

The device resets the bus with the I2C START condition

for reads. When the R/W bit is set to 1, the deserializers

transmit data to the master, thus the master is reading

from the device.

Format for Writing

Writes to the deserializers comprise the transmission of

the slave address with the R/W bit set to zero, followed

by at least 1 byte of information. The first byte of informa-

tion is the register address or command byte. The register

address determines which register of the device is to be

written by the next byte, if received. If a STOP (P) condi-

tion is detected after the register address is received, the

device takes no further action beyond storing the register

address (Figure 51). Any bytes received after the register

address are data bytes. The first data byte goes into the

data bytes go into subsequent registers (Figure 52). If

multiple data bytes are transmitted before a STOP con-

dition, these bytes are stored in subsequent registers

because the register addresses autoincrement.

Figure 51. Format for I2C Write

Figure 52. Format for Write to Multiple Registers

ADDRESS = 0x80

0 = WRITE

D7 D6 D5 D4

D3 D2 D1 D0

S = START BIT

P = STOP BIT

A = ACK

D_ = DATA BIT

S = START BIT

P = STOP BIT

A = ACK

N = NACK

D_ = DATA BIT

ADDRESS = 0x80

0 = WRITE

48SWTQFN-EP Datasheet(PDF) 65 Page - Maxim Integrated Products

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