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48SWTQFN-EP Datasheet(PDF) 28 Page - Maxim Integrated Products

Part # 48SWTQFN-EP
Description  3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output
PDF  103 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

48SWTQFN-EP Datasheet(HTML) 28 Page - Maxim Integrated Products

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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
www.maximintegrated.com
Maxim Integrated │ 28
Output Bit Map
The input/output bit width depends on settings of the bus
width pin (BWS) and the CSI-2 output mode. Table 4 and
Table 3 list the bit map for video signals. Table 4 lists the
bit map for control signals. Unused control output bits are
pulled low.
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive
twisted-pair cable and single-ended CML to drive
coaxial cable with programmable pre/deemphasis and
AC-coupling. The deserializer uses AC-coupling and
programmable channel equalization.
Input data is scrambled and then 8b/10b coded (9b/10b
in high-bandwidth mode). The deserializer recovers the
embedded serial clock, then samples, decodes, and
descrambles the data. In 24-bit mode, the first 21 bits
contain 18 bits of video data and 3 bits of control data
(HS/VS/DE). In 32-bit mode, the first 29 bits contain
24 bits of video data, 3 bits of control data (HS/VS/DE)
and two bits of control data (CNTL1/CNTL2). In high-
bandwidth mode, the first 24 bits contain video data, or
special control-signal packets. In all modes, the last 3 bits
contain the embedded audio channel, the embedded for-
ward control channel, and the parity bit of the serial word
(Figure 14, Figure 15, Figure 16).
GMSL-to-CSI-2 Conversion and Output
The GMSL deserializer recovers the clock from the
serialized input signals and extracts the video, audio,
and control. Video data are packetized to according to
MIPI CSI-2 packet formats and sent out through the MIPI
DPHY serial lanes.
Video Data Operation
The device converts the video control signal VS to the
CSI-2 Frame Start or Frame End short packet (Figure 17).
The converter also assembles the pixel color data into
the CSI-2 long packets based on the formats and/or pixel
count programmed by the user (Figure 18, Figure 19,
Figure 20, Figure 21, Figure 22, Figure 23, Figure 24,
Figure 25, Figure 26, Figure 27, Figure 28, Figure 29,
Figure 30, and Figure 31). DE low period needs to be a
minimum 200 PCLK cycles to accommodate SOT and
EOT during the DE blanking period.
Table 1. Device Address Defaults (Register 0x00, 0x01)
*X = 0 for the serializer address, X = 1 for the deserializer address.
**CX/TP determine the serial-cable type CX/TP = open addresses only for coax mode.
PIN
DEVICE ADDRESS
(BIN)
SERIALIZER
DEVICE
ADDRESS
(hex)
DESERIALIZER
DEVICE
ADDRESS
(hex)
CX/TP
ADD2
ADD1
ADD0
D7
D6
D5
D4
D3
D2
D1
D0
High/Low
Low
Low
Low
1
0
0
X*
0
0
0
R/W
80
90
High/Low
Low
Low
High
1
0
0
X*
0
1
0
R/W
84
94
High/Low
Low
High
Low
1
0
0
X*
1
0
0
R/W
88
98
High/Low
Low
High
High
0
1
0
X*
0
1
0
R/W
44
54
High/Low
High
Low
Low
1
1
0
X*
0
0
0
R/W
C0
D0
High/Low
High
Low
High
1
1
0
X*
0
1
0
R/W
C4
D4
High/Low
High
High
Low
1
1
0
X*
1
0
0
R/W
C8
D8
High/Low
High
High
High
0
1
0
X*
1
0
0
R/W
48
58
Open**
Low
Low
Low
1
0
0
X*
0
0
X*
R/W
80
92
Open**
Low
Low
High
1
0
0
X*
0
1
X*
R/W
84
96
Open**
Low
High
Low
1
0
0
X*
1
0
X*
R/W
88
9A
Open**
Low
High
High
0
1
0
X*
0
1
X*
R/W
44
56
Open**
High
Low
Low
1
1
0
X*
0
0
X*
R/W
C0
D2
Open**
High
Low
High
1
1
0
X*
0
1
X*
R/W
C4
D6
Open**
High
High
Low
1
1
0
X*
1
0
X*
R/W
C8
DA
Open**
High
High
High
0
1
0
X*
1
0
X*
R/W
48
5A



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