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48SWTQFN-EP Datasheet(PDF) 49 Page - Maxim Integrated Products |
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48SWTQFN-EP Datasheet(HTML) 49 Page - Maxim Integrated Products |
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49 / 103 page  MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 49 Clock Operation The GMSL deserializer recovers the pixel clock (PCLK) from the serial input. This pixel clock is used to time various functions of the device such as the control sig- nals and MCLK. The pixel, along with the CSI data type, determines the CSI HS clock (CLK+/-) When the clocks are stable, the LOCK pin goes high and the clock trans- mitter starts the SOT, HS prepare and HS zero sequences and transmits the HS clock in HS differential mode. If the device loses of lock, the clock lane is disabled, and the clock transmitter pulls the line to stop state (LP-11). Data-Rate Selection and CSI-2 Clock Limitations Three factors affect the overal useable clock range of the GMSL deserializers: The valid clock range of the GMSL serial input, the MIPI CSI-2 output, and the data bit width. Table 5 lists the valid PCLK range at various CSI-2 output modes. Table 6 shows the valid CSI-2 output-channel bit rate. Table 3. Video Output Map (RAW and User Defined) 1. Refer to the GMSL serializer data sheet for details. 2. RAW datatype defaults to single load. Set INPUTBW = 1 to use double input mode (output sequence PA0, PB0, PA1, PB1). 3. Data type available when BWS = high or open, only. GMSL INPUT BITS1 RAW (DOUBLE LOAD2) RAW (SINGLE LOAD2) USER DEFINED 8-BIT 10-BIT3 12-BIT3 8-BIT 10-BIT 12-BIT 14-BIT 24-BIT3 8-BIT DIN0 PA0 PA0 PA0 P0 P0 P0 P0 UA0 U0 DIN1 PA1 PA1 PA1 P1 P1 P1 P1 UA1 U1 DIN2 PA2 PA2 PA2 P2 P2 P2 P2 UA2 U2 DIN3 PA3 PA3 PA3 P3 P3 P3 P3 UA3 U3 DIN4 PA4 PA4 PA4 P4 P4 P4 P4 UA4 U4 DIN5 PA5 PA5 PA5 P5 P5 P5 P5 UA5 U5 DIN6 PA6 PA6 PA6 P6 P6 P6 P6 UB0 U6 DIN7 PA7 PA7 PA7 P7 P7 P7 P7 UB1 U7 DIN8 PB0 PA8 PA8 — P8 P8 P8 UB2 — DIN9 PB1 PA9 PA9 — P9 P9 P9 UB3 — DIN10 PB2 PB0 PA10 — — P10 P10 UB4 — DIN11 PB3 PB1 PA11 — — P11 P11 UB5 — DIN12 PB4 PB2 PB0 — — — P12 UC0 — DIN13 PB5 PB3 PB1 — — — P13 UC1 — DIN14 PB6 PB4 PB2 — — — — UC2 — DIN15 PB7 PB5 PB3 — — — — UC3 — DIN16 — PB6 PB4 — — — — UC4 — DIN17 — PB7 PB5 — — — — UC5 — DIN18 HS HS HS HS HS HS HS HS HS DIN19 VS VS VS VS VS VS VS VS VS DIN20 DE DE DE DE DE DE DE DE DE DIN21 — PB8 PB6 — — — — UA6 — DIN22 — PB9 PB7 — — — — UA7 — DIN23 — — PB8 — — — — UB6 — DIN24 —- — PB9 — — — — UB7 — DIN25 — — PB10 — — — — UC6 — DIN26 — — PB11 — — — — UC7 — |
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