48SWTQFN-EP datasheet(85/103 Pages) MAXIM

85 / 103 page

MAX9288/MAX9290

3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated │ 85

For the fault-detection circuit, select the resistor’s power

rating to handle a short to the battery. In coax mode,

leave the unused line-fault inputs unconnected. To detect

the short-together case, refer to Application Note 4709:

GMSL Line-Fault Detection. Table 23 lists the mapping

for line fault types

Internal Input Pulldowns

The control and configuration inputs (except three-level

inputs) include a pulldown resistor to GND. External

pulldown resistors are not needed.

Choosing I2C/UART Pullup Resistors

I2C and UART open-drain lines require a pullup resistor

to provide a logic-high level. There are tradeoffs between

power dissipation and speed, and a compromise may

be required when choosing pullup resistor values. Every

device connected to the bus introduces some capacitance

even when the device is not in operation. I2C specifies

300ns rise times (30% to 70%) for fast mode, which

is defined for data rates up to 400kbps (see the I2C

specifications in the AC Electrical Characteristics table

for details). To meet the fast-mode rise-time requirement,

choose the pullup resistors so that rise time tR = 0.85

x RPULLUP x CBUS < 300ns. The waveforms are not

recognized if the transition time becomes too slow. The

device supports I2C/UART rates up to 1Mbps.

AC-Coupling

AC-coupling isolates the receiver from DC voltages up

to the voltage rating of the capacitor. Capacitors at the

serializer output and at the deserializer input are needed

for proper link operation and to provide protection if either

end of the cable is shorted to a battery. AC-coupling

blocks low-frequency ground shifts and low-frequency

common-mode noise.

Selection of AC-Coupling Capacitors

Voltage droop and the digital sum variation (DSV) of

transmitted symbols cause signal transitions to start from

different voltage levels. Because the transition time is fixed,

starting the signal transition from different voltage levels

causes timing jitter. The time constant for an AC-coupled

link needs to be chosen to reduce droop and jitter to an

acceptable level. The RC network for an AC-coupled link

consists of the CML/coax receiver termination resistor

(RTR), the CML/coax driver termination resistor (RTD),

and the series AC-coupling capacitors (C). The RC time

constant for four equal-value series capacitors is (C x

(RTD + RTR))/4. RTD and RTR are required to match the

transmission line impedance (usually 100Ω differential,

50Ω single ended). This leaves the capacitor selection to

change the system time constant. Use at 0.22μF (using

power over coax or legacy reverse control channel), 47nF

(using high-immunity reverse control channel without

power over coax), or larger high-frequency surface-

mount ceramic capacitors, with sufficient voltage rating

to withstand a short to battery, to pass the lower

speed reverse control-channel signal. Use capacitors

with a case size less than 3.2mm x 1.6mm to have lower

parasitic effects to the high-speed signal.

Power-Supply Circuits and Bypassing

The deserializers use an AVDD18 and DVDD18 of 1.7V

to 1.9V and an AVDD3 of 3.0V to 3.6V. All single-ended

inputs and outputs except for the serial input derive power

from an IOVDD of 1.7V to 3.6V that scale with IOVDD.

Proper voltage-supply bypassing is essential for high-

frequency circuit stability.

Power-Supply Table

Power-supply currents shown in the DC Electrical

Characteristics table is measured at VIOVDD = 3.6V. If

using a different IOVDD voltage, the IOVDD worst-case

supply current will vary. HDCP operation (MAX9290 only)

draws additional current. This is shown in Table 24.

Cables and Connectors

Interconnect for CML typically has a differential

impedance of 100Ω. Use cables and connectors that

have matched differential impedance to minimize imped-

ance discontinuities. Coax cables typically have a

characteristic impedance of 50Ω, contact the factory for

75Ω operation). Table 24 lists the suggested cables and

connectors used in the GMSL link.

Board Layout

Separate LVCMOS logic signals and CML/coax high-

speed signals to prevent crosstalk. Use a four-layer PCB

with separate layers for power, ground, CML/coax, and

LVCMOS logic signals. Layout PCB traces close to each

other for a 100Ω differential characteristic impedance for

STP. The trace dimensions depend on the type of trace

used (microstrip or stripline). Note that two 50Ω PCB

traces do not have 100Ω differential impedance when

brought close together—the impedance goes down when

the traces are brought closer. Use a 50Ω trace for the

single-ended output when driving coax.

Route the PCB traces for differential CML channel in

parallel to maintain the differential characteristic imped-

ance. Avoid vias. Keep PCB traces that make up a

differential pair equal length to avoid skew within the

differential pair.

48SWTQFN-EP Datasheet(PDF) 85 Page - Maxim Integrated Products

48SWTQFN-EP Datasheet(HTML) 85 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL