CS47L85 datasheet(104/370 Pages) CIRRUS

104 / 370 page

CS47L85

104

Rev 4.3

Note that the PWM signal generators cannot be selected as input to the digital mixers or signal processing functions within

the CS47L85 digital core.

PWM1MIX_VOL2

PWM1MIX_VOL3

PWM1MIX_VOL4

PWM1MIX_VOL1

PWM1MIX_SRC1

PWM1MIX_SRC3

PWM1MIX_SRC4

PWM1MIX_SRC2

GPIO

(GPn_FN = 48h)

PWM1

PWM1_ENA

PWM1_OVD

PWM1_LVL

PWM2MIX_VOL2

PWM2MIX_VOL3

PWM2MIX_VOL4

PWM2MIX_VOL1

PWM2MIX_SRC1

PWM2MIX_SRC3

PWM2MIX_SRC4

PWM2MIX_SRC2

GPIO

(GPn_FN = 49h)

PWM2

PWM2_ENA

PWM2_OVD

PWM2_LVL

PWM_RATE

PWM_CLK_SEL

When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer.

When PWMn_OVD = 1, the PWM duty cycle is set by PWMn_LVL.

The PWM sample rate and clocking frequency are selected using PWM_RATE and PWM_CLK_SEL.

Figure 36 Digital Core Pulse Width Modulation (PWM) Generator

The PWM1 and PWM2 mixer control registers (see Figure 36) are located at register addresses R1600 (640h) through to

R1615 (64Fh).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be

configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are

available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous

Sample Rate Converter (ISRC)

”.

The PWM generators should be kept disabled (PWMn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all

digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting

other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The PWM sample rate (cycle time) is configured using the PWM_RATE register - see Table 22. Note that sample rate

conversion is required when linking the PWM generators to any signal chain that is asynchronous and/or configured for a

different sample rate.

The PWM_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing a new value to PWM_RATE. A minimum delay of 125us should

be allowed between clearing the *_SRCn registers and writing to the PWM_RATE register. See Table 22 for further details.

The PWM generators are enabled using PWM1_ENA and PWM2_ENA respectively, as described in Table 21.

Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path; a

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