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STAC9752 Datasheet(PDF) 59 Page - Integrated Device Technology |
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STAC9752 Datasheet(HTML) 59 Page - Integrated Device Technology |
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59 / 95 page ![]() STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING IDT™ 59 STAC9752/9753 REV 3.3 1206 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.18.1. Ready Status The lower half of this register is read only status, a 1 indicating that each subsection is “ready”. Ready is defined as the subsection's ability to perform in its nominal state. When this register is writ- ten, the bit values that come in on AC-Link will have no effect on read-only bits 0-7. When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. When this register is written, the bit values that come in on AC-Link will have no effect on read-only bits 0-7. 8.1.18.2. Powerdown Controls The STAC9752/9753 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). See the section “Low Power Modes” for more information. 8.1.18.3. External Amplifier Power Down Control Output The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output, pin 45, and produces a logical 1 when this bit is set to logic high. This function is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility. EAPD can also act as a GPIO. See Section 8.4.11: page77. The GPIO controls in Section 8.2: page64 have no effect on EAPD. 8.1.19. Extended Audio ID (28h) Default: 0A05h 8 0 PR0 0 = ADC powered up 1 = ADC powered down 7:4 0 RESERVED Bit not used, should read back 0 3 1 REF Read Only --- VREF status 1 = VREFs enabled 2 1 ANL Read Only ---- ANALOG MIXERS, etc. Status 1 = Analog Mixers ready. 1 1 DAC Read Only ---- DAC Status 1 = DAC ready to playback 0 1 ADC Read Only ---- ADC Status 1 = ADC ready to record D15 D14 D13 D12 D11 D10 D9 D8 ID1 ID0 RESERVED AMAP RSVD D7 D6 D5 D4 D3 D2 D1 D0 RESERVED DSA1 DSA0 RSVD SPDIF RSVD VRA Bit(s) Reset Value Name Description |
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