STAC9752 datasheet(86/95 Pages) IDT

86 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

12.1. Digital I/O

These signals connect the STAC9752/9753 to its AC'97 controller counterpart, an external crystal,

multi-CODEC selection and external audio amplifier.

Note: Pins 31, 33, and 34 are NO CONNECTS.

Table 32. Digital Connection Signals

Pin Name

Pin #

Type

Description

XTL_IN

24.576 MHz Crystal or External Clock Source

XTL_OUT

I/O

24.576 MHz Crystal

SDATA_OUT

Serial, time division multiplexed, AC'97 input stream

BIT_CLK

I/O

12.288 MHz serial data clock

SDATA_IN

Serial, time division multiplexed, AC'97 output stream

SYNC

48 KHz fixed rate sample sync

RESET#

AC'97 Master H/W Reset

N.C.

IDT Internal Test mode only.

N.C.

IDT Internal Test mode only

N.C.

I/O

IDT Internal Test mode only

GPIO0

I/O

General Purpose I/O

GPIO1

I/O

General Purpose I/O

CID0

Multi-CODEC ID select – bit 0

CID1

Multi-CODEC ID select – bit 1

EAPD

I/O

External Amplifier Power Down/GPIO

SPDIF

I/O

SPDIF digital output

Pin 48: To Enable SPDIF, use an 1 K

Ω - 10 KΩ external

pulldown. To Disable SPDIF, use an 1K

Ω - 10KΩ external

pullup. Do NOT leave Pin 48 floating.

STAC9752 Datasheet(PDF) 86 Page - Integrated Device Technology

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