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STAC9752 Datasheet(PDF) 63 Page - Integrated Device Technology |
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STAC9752 Datasheet(HTML) 63 Page - Integrated Device Technology |
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63 / 95 page  STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING IDT™ 63 STAC9752/9753 REV 3.3 1206 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.21. PCM DAC Rate Registers (2Ch and 32h) The internal sample rate for the DACs and ADCs are controlled by a value in these read/write regis- ters (that contain a 16-bit unsigned value between 0 and 65535) representing the conversion rate in Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported, that value will be echoed back when read; otherwise the closest (higher in the case of a tie) sample rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are supported for record and playback. Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) will be loaded with BB80h (48 KHz). If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48 KHz. 8.1.22. PCM DAC Rate (2Ch) Default: BB80h (see table20: page63) 8.1.23. PCM LR ADC Rate (32h) Default: BB80h (see table20: page63) Table 19. AMAP compliant CODEC ID Function SPSA = 00 slot assignment SPSA = 01 slot assignment SPSA = 10 slot assignment SPSA = 11 slot assignment 00 2-ch Primary w/SPDIF 3 & 4 7 & 8* 6 & 9 10 & 11 01 2-ch Dock CODEC w/SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11 10 +2-ch Surr w/ SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11 11 +2-ch Cntr/LFE w/ SPDIF 3 & 4 7 & 8 6 & 9 10 & 11* Note: * indicates the default slot assignment Table 20. Hardware Supported Sample Rates Sample Rate SR[15:0] Value 8 KHz 1F40h 11.025 KHz 2B11h 16 KHz 3E80h 22.05 KHz 5622h 32 KHz 7D00h 44.1 KHz AC44h 48 KHz BB80h D15 D14 D13 D12 D11 D10 D9 D8 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 D7 D6 D5 D4 D3 D2 D1 D0 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 D15 D14 D13 D12 D11 D10 D9 D8 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 D7 D6 D5 D4 D3 D2 D1 D0 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 |
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