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STAC9752 Datasheet(PDF) 69 Page - Integrated Device Technology |
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STAC9752 Datasheet(HTML) 69 Page - Integrated Device Technology |
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69 / 95 page ![]() STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING IDT™ 69 STAC9752/9753 REV 3.3 1206 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4. STAC9752/9753 Paging Registers The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of regis- ters. The registers currently used in the paging are 60h to 6Eh. For additional information about the Extended CODEC Registers, please refer to Section 8.3: page68. One of two pages can be made active at any time, set in Register 24h. Register 24h is the Audio Interrupt and Paging Register. Additional details about Register 24h is located in Section 8.1.17: page57. If page 00h is active, registers 60h to 6Eh are Vendor Specific. If page 01h is active, registers 60h to 6Eh have the following functionality: 8.4.1. CODEC Class/Rev (60h Page 01h) Register 24h must be set to Page 01h to access this register. Default: 12xxh Reg NAME FUNCTION Location 60h CODEC Class/Revision Provides the CODEC Class and a Vendor specified revision identifier. 8.4.1: page69 62h PCI SVID Allows for population by the system BIOS to identify the PCI Sub System Vendor ID. 8.4.2: page70 64h PCI SSID Allows for population by the system BIOS to identify the PCI Sub System ID. Note:: page70 66h Function Select Provides the type of audio function being selected and which jack conductor the selected value is measured from. Note:: page70 68h Function Information Includes information about Gain, Inversion, Buffer delays, Information Validity, and Function Information presence. 8.4.5: page72 6Ah Sense Register Includes information about the connector/jack location, Input verses Output sensing, the order of the sense results, and the IDT specific sense results. 8.4.7: page74 6Ch Reserved 6Eh Reserved D15 D14 D13 D12 D11 D10 D9 D8 RESERVED CL4 CL3 CL2 CL1 CL0 D7 D6 D5 D4 D3 D2 D1 D0 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0 Bit(s) Reset Value Name Description 15-13 Reserved Reserved-not defined |
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