PM7347 datasheet(37/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Pin Name

Type

No.

Function

TOH

Input

When configured for DS3 operation, Transmit DS3/E3/J2

Overhead Data (TOH) contains the overhead bits (C, F,

X, P, and M) that may be inserted in the transmit DS3

stream.

When configured for G.832 E3 operation, TOH contains

the overhead bytes (FA1, FA2, EM mask, TR, MA, NR,

and GC) that may be inserted in the transmit G.832 E3

stream.

When configured for G.751 E3 operation, TOH contains

the overhead bits (RAI, National Use, Stuff Indication,

and Stuff Opportunity) that may be inserted in the

transmit G.751 E3 stream.

When configured for J2 operation, TOH contains the

overhead bits (TS97, TS98, Framing, X1-3, A, M, E1-5)

that may be inserted in the transmit J2 stream.

If TOHINS is a logic one, the TOH input has precedence

over the internal datalink transmitter, or any other internal

TOHCLK.

TOHFP

Output

The Transmit DS3/E3/J2 Overhead Frame Position

(TOHFP) is used to align the individual overhead bits in

the transmit overhead data stream, TOH, to the DS3 M-

frame or the E3 frame.

For DS3, TOHFP is high during the X1 overhead bit

position in the TOH stream. For G.832 E3, TOHFP is

high during the first bit of the FA1 byte. For G.751 E3,

TOHFP is high during the RAI overhead bit position in

the TOH stream. For J2, TOHFP is high during the first

bit of timeslot 97 in the first frame of a 4-frame

multiframe).

TOHFP is updated on the falling edge of TOHCLK.

TOHCLK

Output

The Transmit DS3/E3/J2 Overhead Clock (TOHCLK) is

active when a DS3, E3, or J2 stream is being processed.

TOHCLK is nominally a 526 kHz clock for DS3, a 1.072

MHz clock for G.832 E3, a 1.074 MHz clock for G.751

E3, and a gapped 6.312 MHz clock with an average

frequency of 168 kHz for J2.

TOHFP is updated on the falling edge of TOHCLK. TOH,

and TOHINS are sampled on the rising edge of

TOHCLK.

REF8KI

Input

The PLCP frame rate is locked to an external 8 kHz

reference applied on Reference 8 kHz Input (REF8KI).

An internal phase-frequency detector compares the

transmit PLCP frame rate with the externally applied 8

kHz reference and adjusts the PLCP frame rate.

The REF8KI input must transition high once every 125

µs

for correct operation. The REF8KI input is treated as an

asynchronous signal and must be “glitch-free”. If the

LOOPT register bit is logic one, the PLCP frame rate is

locked to the RPOHFP signal instead of the REF8KI

input.

PM7347 Datasheet(PDF) 37 Page - PMC-Sierra, Inc

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