PM7347 datasheet(65/341 Pages) PMC

65 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Figure 6 Cell delineation State Diagram

HUNT

PRESYNC

SYNC

Correct HCS

(bit by bit)

Incorrect HCS

(cell by cell)

DELTA consecutive

correct HCS's

(cell by cell)

ALPHA consecutive

incorrect HCS's

(cell by cell)

The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA

determines the robustness against false misalignments due to bit errors. DELTA determines the

robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and

DELTA is chosen to be 6 as recommended in ITU-T Recommendation I.432. These values result

in a maximum average time to frame of 127 µs for a DS3 stream carrying ATM cells directly

mapped into the DS3 information payload.

LCD is detected by counting the number of incorrect cells while in the HUNT state. The counter

value is stored in the RXCP-50 LCD Count Threshold Register. The threshold has a default value

of 360 which results in:

• A DS3 application detection time of 3.5 ms.

• An E3 G.832 application detection time of 4.5 ms.

• An E3 G.751 application detection time of 5.0 ms.

• A J2 application time of 24.8ms, an E1 application detection time of 77 ms.

• A DS1 application detection time of 100 ms.

If the counter value is set to zero, the LCD output signal is asserted for every incorrect cell.

10.9

PRGD Pseudo-Random Sequence Generator/Detector

The Pseudo-Random Sequence Generator/Detector (PRGD) block is a software programmable

test pattern generator, receiver, and analyzer. Two types of test patterns (pseudo-random and

repetitive) conform to ITU-T O.151.

PM7347 Datasheet(PDF) 65 Page - PMC-Sierra, Inc