REF5045 datasheet(26/62 Pages) TI2

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BUSY

D17

D16

Acquiring

Sample N

Converting

Sample N

Conversion Result of Sample N Clocked-out

while Acquiring Sample N+1

End-of-Conversion

ADC

STATE

DOUT

SCLK

CONVST

1/fsample

tACQ

tconv-max

tconv-min

SDO Pulled-up

CONVST = 0

DIN = DVDD

CONVST

SCLK

DOUT

CNV

CLK

SDI

DIN

ADC

Digital Host

DVDD

IRQ

ADS8881

SBAS547D – MAY 2013 – REVISED AUGUST 2015

www.ti.com

Product Folder Links: ADS8881

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Device Functional Modes (continued)

10.4.1.2 3-Wire CS Mode With a Busy Indicator

This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an

interrupt-driven data transfer is desired. In this interface option, DIN can be connected to DVDD and CONVST

functions as CS (as shown in Figure 52). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the

digital host is held high when DOUT goes to 3-state. As shown in Figure 53, a CONVST rising edge forces

DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is

done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning

as CS) can be pulled low after the start of the conversion to select other devices on the board. However,

CONVST must be pulled low before the minimum conversion time (tconv-min) elapses and must remain low until

the maximum possible conversion time (tconv-max) elapses. A low level on the CONVST input at the end of a

conversion ensures the device generates a busy indicator.

Figure 52. Connection Diagram: 3-Wire CS Mode With a Busy Indicator

Figure 53. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (DIN = 1)

When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3-

state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a high-

to-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent

SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling

edges. For slow sampling rates and SCLK frequency

≤ 36 MHz, data can be read at either SCLK falling or rising

edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in

the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 19th SCLK falling edge or when

CONVST goes high, whichever occurs first.

REF5045 Datasheet(PDF) 26 Page - Texas Instruments

REF5045 Datasheet(HTML) 26 Page - Texas Instruments

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