REF5045 datasheet(47/62 Pages) TI2

47 / 62 page

1PF

10PF

Differential

Inputs

DVDD

10: DVDD

9: SDI

8: SCLK

7: SDO

6: CONVST

GND

5: GND

4: AINN

3: AINP

2: AVDD

1: REF

0.1O t 0.47O

REF

GND

47O

GND

Positive Input

Negative Input

SDO

ADS8881

www.ti.com

SBAS547D – MAY 2013 – REVISED AUGUST 2015

Product Folder Links: ADS8881

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13 Layout

13.1 Layout Guidelines

Figure 77 shows a board layout example for the device. Appropriate layout that interconnects accompanying

capacitors and converters with low inductance is critical for achieving optimum performance. Thus, a PCB board

with at least four layers is recommended to keep all critical components on the top layer and interconnected to a

solid (low inductance) analog ground plane at the subsequent inner layer using 15-mil vias. Avoid crossing digital

lines with the analog signal path and keep the analog input signals and the reference input signals away from

noise sources. As shown in Figure 77, the analog input and reference signals are routed on the left side of the

board and the digital connections are routed on the right side of the device.

As a result of dynamic currents during conversion and data transfer, each supply pin (AVDD and DVDD) must

have a decoupling capacitor to keep the supply voltage stable. To maximize decoupling capabilities, inductance

between each supply capacitor and the supply pin of the converter is kept less than 5 nH by placing the

capacitor within 0.2-inches from the pin and connecting it with 20-mil traces and a 15-mil grounding via, as

shown in Figure 77. TI recommends using one 1-μF ceramic capacitor at each supply pin. Avoid placing vias

between the supply pin and its decoupling capacitor.

Dynamic currents are also present at the REF pin during the conversion phase and very good decoupling is

critical to achieve optimum performance. The inductance between the reference capacitor and the REF pin is

kept less than 2 nH by placing the capacitor within 0.1-inches from the pin and connecting it with 20-mil traces

and multiple 15-mil grounding vias, as shown in Figure 77. A single, 10-μF, X7R-grade, 0805-size, ceramic

capacitor with at least a 10-V rating is recommended for good performance over the rated temperature range.

Avoid using additional lower value capacitors because the interactions between multiple capacitors may affect

the ADC performance at higher sampling rates. A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with

the reference capacitor (as shown in Figure 77) keeps the overall impedance low and constant, especially at very

high frequencies.

The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,

COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG

(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature

changes.

13.2 Layout Example

Figure 77. Recommended Layout

REF5045 Datasheet(PDF) 47 Page - Texas Instruments

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