REF5045 datasheet(28/62 Pages) TI2

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œœ

D17

D16

DOUT

SCLK

CONVST

1/fsample

tACQ

tconv-max

Acquiring

Sample N

Converting

Sample N

End-of-

Conversion

ADC

STATE

tconv-min

œœ

D17

œœ

D16

DIN

(ADC 1)

Acquiring Sample N+1

Read Sample N

ADC 1

Read Sample N

ADC 2

DIN

(ADC 2)

DIN = 1

CS1

CNV

CS2

SDI

CLK

CONVST

DIN

DOUT

SCLK

CONVST

DIN

DOUT

SCLK

ADC #1

ADC #2

Digital Host

ADS8881

SBAS547D – MAY 2013 – REVISED AUGUST 2015

www.ti.com

Product Folder Links: ADS8881

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Device Functional Modes (continued)

When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS)

can be brought low after the maximum conversion time (tconv-max) elapses. On the DIN falling edge, DOUT comes

out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK

falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges.

For slow sampling rates and SCLK frequency

≤ 36 MHz, data can be read at either SCLK falling or rising edges.

Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the

data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 18th SCLK falling edge or when DIN goes

high, whichever occurs first.

As shown in Figure 56, multiple devices can be hooked together on the same data bus. In this case, as shown in

Figure 57, the DIN of the second device (functioning as CS for the second device) can go low after the first

device data are read and the DOUT of the first device is in 3-state.

Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.

Figure 56. Connection Diagram: Two ADCs With 4-Wire CS Mode Without a Busy Indicator

Figure 57. Interface Timing Diagram: Two ADCs With 4-Wire CS Mode

REF5045 Datasheet(PDF) 28 Page - Texas Instruments

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