REF5045 datasheet(33/62 Pages) TI2

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ADS8881

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SBAS547D – MAY 2013 – REVISED AUGUST 2015

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Device Functional Modes (continued)

At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift

host. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal

shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT

pin. Therefore, the digital host receives the interrupt signal followed by the data of ADC N followed by the data of

ADC N–1, and so on (in MSB-first fashion). A total of (18 × N) + 1 SCLK falling edges are required to capture the

outputs of all N devices in the chain. Fast sampling rates require a high-frequency SCLK and data must be read

at the SCLK falling edges. For slow sampling rates and SCLK frequency

≤ 36 MHz, data can be read at either

SCLK falling or rising edges. Note that with any SCLK frequency, reading data at the SCLK falling edge requires

the digital host to clock in the data during the th_CK_DO-min time frame. Note that the busy indicator bits of ADC 1 to

ADC N–1 do not propagate to the next device in the chain.

NOTE: For SCLK

≤ 36 MHz, SPI mode-3 (CPOL = 1, CPHA = 1) allows reading the conversion results of N

ADCs in 18 × N SCLK cycles because the busy indicator bit is not clocked in by the host.

11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation

section details some general principles for designing these circuits, followed by some application circuits

designed using the ADS8881.

11.1.1 ADC Reference Driver

The external reference source to the ADS8881 must provide low-drift and very accurate voltage for the ADC

reference input and support the dynamic charge requirements without affecting the noise and linearity

performance of the device. The output broadband noise of most references can be in the order of a few hundred

μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage

reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz.

After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that

can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the

voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each

conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 48) for regulating the

voltage at the reference input of the ADC. The amplifier selected to drive the reference pin must have an

extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC

reference pin without any stability issues.

11.1.2 ADC Input Driver

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel

RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides

a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate

the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing

filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is

critical to meet the linearity and noise performance of a high-precision, 18-bit ADC such as the ADS8881.

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