REF5045 datasheet(29/62 Pages) TI2

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BUSY

D17

D16

DOUT

SCLK

DIN

CONVST

1/fsample

tACQ

tconv-max

Acquiring

Sample N

Converting

Sample N

Conversion Result of Sample N Clocked-out

while Acquiring Sample N+1

ADC

STATE

SDO Pulled-up

tconv-min

DIN =0

CONVST

SCLK

DOUT

CNV

CLK

SDI

DIN

ADC

Digital Host

IRQ

DVDD

ADS8881

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SBAS547D – MAY 2013 – REVISED AUGUST 2015

Product Folder Links: ADS8881

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Device Functional Modes (continued)

10.4.1.4 4-Wire CS Mode With a Busy Indicator

This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an

interrupt-driven data transfer is desired. In this interface option, the analog sample is least affected by clock jitter

because the CONVST signal (used to sample the input) is independent of the data read operation. In this

interface option, DIN is controlled by the digital host and functions as CS (as shown in Figure 58). The pull-up

resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As

shown in Figure 59, when DIN is high, a CONVST rising edge selects CS mode, forces DOUT to 3-state,

samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST

must be held high from the start of the conversion until all data bits are read. Conversion is done with the internal

clock and continues regardless of the state of DIN. As a result, DIN (acting as CS) can be pulled low to select

other devices on the board. However, DIN must be pulled low before the minimum conversion time (tconv-min)

elapses and remains low until the maximum possible conversion time (tconv-max) elapses. A low level on the DIN

input at the end of a conversion ensures the device generates a busy indicator.

Figure 58. Connection Diagram: 4-Wire CS Mode With a Busy Indicator

Figure 59. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator

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