REF5045 datasheet(11/62 Pages) TI2

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D17

D16

D15

DOUT

SCLK

DIN

CONVST

1/fsample

tACQ

tconv-max

td-DI-DO

twl-CNV

tsu-DI-CNV

td-DI-DOhz

twh-DI-min

ADS8881

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SBAS547D – MAY 2013 – REVISED AUGUST 2015

Product Folder Links: ADS8881

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8.7 Timing Requirements: 4-Wire Operation

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.

MIN

TYP

MAX UNIT

tACQ

Acquisition time

290

tconv

Conversion time

TA in the range –40°C to 85°C

500

710

TA in the range 0°C to 70°C

500

700

tconv

Conversion time

500

1/fsample

Time between conversions

1000

twh-DI

Pulse duration: DIN high

twl-CNV

Pulse width: CONVST low

td-DI-DO

Delay time: DIN low to MSB valid

12.3

td-DI-DOhz

Delay time: DIN high or last SCLK falling edge to DOUT 3-state

13.2

tsu-DI-CNV

Setup time: DIN high to CONVST rising edge

7.5

th-DI-CNV

Hold time: DIN high from CONVST rising edge (see Figure 63)

Figure 2. 4-Wire Operation: DIN Functions as Chip Select

NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option.

However, the timing parameters specified in Timing Requirements: 4-Wire Operation are also applicable for the

4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional

Modes section for specific details for each interface option.

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