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REF5045 Datasheet(PDF) 31 Page - Texas Instruments |
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REF5045 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 62 page ![]() œœ œœ œœ D17 D0 1 18 D1 D16 17 DOUT-1 & DIN-2 SCLK 2 CONVST 1/fsample tACQ tconv-max Acquiring 6DPSOH µQ¶ Converting 6DPSOH µQ¶ End-of- Conversion ADC STATE tconv-min œœ 19 36 35 20 $FTXLULQJ 6DPSOH µQ+1¶ ADC 2 GDWD IRU VDPSOH µQ¶ ADC 1 GDWD IRU VDPSOH µQ¶ DOUT-2 œœ D17 œœ œœ D17 D0 D1 D16 œœ œœ D0 D1 D16 DIN-1 = LOW ADC 1 data ADC 2 data ADC 1 data 31 ADS8881 www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Product Folder Links: ADS8881 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Device Functional Modes (continued) As shown in Figure 61, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be low at the CONVST rising edge so that the device does not generate a busy indicator at the end of the conversion. Figure 61. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the digital host receives the data of ADC N, followed by the data of ADC N–1, and so on (in MSB-first fashion). A total of 18 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. |
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