REF5045 datasheet(30/62 Pages) TI2

30 / 62 page

CONVST

DOUT-

SCLK

DIN-

SDI

CLK

CNV

ADC 1

Digital Host

CONVST

DOUT-

SCLK

DIN-

ADC 2

CONVST

DOUT-

SCLK

DIN-

N-1

ADC N

CONVST

DOUT-

N-1

SCLK

DIN-

N-2

ADC N 1

}

ADS8881

SBAS547D – MAY 2013 – REVISED AUGUST 2015

www.ti.com

Product Folder Links: ADS8881

Submit Documentation Feedback

Device Functional Modes (continued)

When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3-

state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a high-

to-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent

SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling

edges. For slow sampling rates and SCLK frequency

≤ 36 MHz, data can be read at either SCLK falling or rising

edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in

the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 19th SCLK falling edge or when DIN

goes high, whichever occurs first. Care must be taken so that CONVST and DIN are not both low together at any

time during the cycle.

10.4.2 Daisy-Chain Mode

Daisy-chain mode is selected if DIN is low at the time of a CONVST rising edge or if DIN and CONVST are

connected together. Similar to CS mode, this mode features operation with or without a busy indicator. The

following sections discuss these interface modes in detail.

10.4.2.1 Daisy-Chain Mode Without a Busy Indicator

This interface option is most useful in applications where multiple ADC devices are used but the digital host has

limited interfacing capability. Figure 60 shows a connection diagram with N ADCs connected in the daisy-chain.

The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the

digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a

single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is connected to GND. The DOUT pin of ADC 1

(DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and so on. The DOUT pin of the last ADC in the chain

(DOUT-N) is connected to the SDI pin of the digital host.

Figure 60. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (DIN = 0)

REF5045 Datasheet(PDF) 30 Page - Texas Instruments

REF5045 Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL