R5F10366ASP datasheet(36/114 Pages) RENESAS

36 / 114 page

RL78/G12

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 36 of 109

Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is

only for the R5F102 products.)

2. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

R5F102 products.))

(5) During communication at same potential (simplified I2C mode)

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

LS (low-speed main) Mode

Unit

MIN.

MAX.

SCLr clock frequency

fSCL

1.8 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

400 Note 1

kHz

1.8 V

≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

300 Note 1

kHz

Hold time when SCLr = “L”

tLOW

1.8 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

1.8 V

≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550

Hold time when SCLr = “H”

tHIGH

1.8 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

1.8 V

≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550

Data setup time (reception)

tSU:DAT

1.8 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1/fMCK + 145 Note 2

1.8 V

≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1/fMCK + 230 Note 2

Data hold time (transmission)

tHD:DAT

1.8 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

355

1.8 V

≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

405

Notes 1.

The value must be equal to or less than fMCK/4.

Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.

Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register

h (POMh).

(Remarks are listed on the next page.)

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