R5F10366ASP datasheet(81/114 Pages) RENESAS

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RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 81 of 109

(4) During communication at same potential (simplified I2C mode)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

SCLr clock frequency

fSCL

Cb = 100 pF, Rb = 3 k

100 Note 1

kHz

Hold time when SCLr = “L”

tLOW

Cb = 100 pF, Rb = 3 k

4600

Hold time when SCLr = “H”

tHIGH

Cb = 100 pF, Rb = 3 k

4600

Data setup time (reception)

tSU:DAT

Cb = 100 pF, Rb = 3 k

1/fMCK + 580 Note 2

Data hold time (transmission)

tHD:DAT

Cb = 100 pF, Rb = 3 k

1420

Notes 1.

The value must be equal to or less than fMCK/4.

Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.

Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register

h (POMh).

Simplified I2C mode connection diagram (during communication at same potential)

RL78

microcontroller

SDAr

SCLr

SDA

SCL

User's device

VDD

Simplified I2C mode serial transfer timing (during communication at same potential)

SDAr

tLOW

tHIGH

tHD:DAT

SCLr

tSU:DAT

1/fSCL

Remarks 1.

Rb [

Ω]:Communication line (SDAr) pull-up resistance

Cb [F]: Communication line (SCLr, SDAr) load capacitance

r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))

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