R5F10366ASP datasheet(92/114 Pages) RENESAS

92 / 114 page

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 92 of 109

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

Unit

MIN.

MAX.

SCLr clock frequency

fSCL

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

100Note1

kHz

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

100Note1

kHz

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

100Note1

kHz

Hold time when SCLr = “L”

tLOW

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

4600

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

4600

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

4650

Hold time when SCLr = “H”

tHIGH

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

2700

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

2400

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1830

Data setup time (reception)

tSU:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK

+ 760 Note2

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK

+ 760 Note2

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1/fMCK

+ 570 Note2

Data hold time (transmission)

tHD:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1420

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1420

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1215

Notes 1.

The value must be equal to or less than fMCK/4.

Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.

Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin

and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode

For VIH and VIL, see the DC

characteristics with TTL input buffer selected.

2. IIC01 and IIC11 cannot communicate at different potential.

(Remarks are listed on the next page.)

R5F10366ASP Datasheet(PDF) 92 Page - Renesas Technology Corp

R5F10366ASP Datasheet(HTML) 92 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL