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R5F10366ASP Datasheet(PDF) 24 Page - Renesas Technology Corp |
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R5F10366ASP Datasheet(HTML) 24 Page - Renesas Technology Corp |
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24 / 114 page  RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 24 of 109 (1) 20-, 24-pin products (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2Note 2 HALT mode HS (High-speed main) modeNote 6 fIH = 24 MHzNote 4 VDD = 5.0 V 440 1210 µA VDD = 3.0 V 440 1210 fIH = 16 MHzNote 4 VDD = 5.0 V 400 950 µA VDD = 3.0 V 400 950 LS (Low-speed main) modeNote 6 fIH = 8 MHzNote 4 VDD = 3.0 V 270 542 µA VDD = 2.0 V 270 542 HS (High-speed main) modeNote 6 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 190 590 µA Resonator connection 260 660 fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 190 590 µA Resonator connection 260 660 LS (Low-speed main) modeNote6 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 110 360 µA Resonator connection 150 416 fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 110 360 µA Resonator connection 150 416 IDD3Note 5 STOP mode TA = –40°C 0.19 0.50 µA TA = +25°C 0.24 0.50 TA = +50°C 0.32 0.80 TA = +70°C 0.48 1.20 TA = +85°C 0.74 2.20 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except temperature condition of the TYP. value is TA = 25°C, other than STOP mode |
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