R5F10366ASP datasheet(89/114 Pages) RENESAS

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RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 89 of 109

(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified SPI (CSI) mode) (slave mode, SCKp... external

clock input)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

Unit

MIN.

MAX.

SCKp cycle time Note 1

tKCY2

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

20 MHz < fMCK

≤ 24 MHz

24/fMCK

8 MHz < fMCK

≤ 20 MHz

20/fMCK

4 MHz < fMCK

≤ 8 MHz

16/fMCK

fMCK

≤ 4 MHz

12/fMCK

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

20 MHz < fMCK

≤ 24 MHz

32/fMCK

16 MHz < fMCK

≤ 20 MHz

28/fMCK

8 MHz < fMCK

≤ 16 MHz

24/fMCK

4 MHz < fMCK

≤ 8 MHz

16/fMCK

fMCK

≤ 4 MHz

12/fMCK

2.4 V

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V

20 MHz < fMCK

≤ 24 MHz

72/fMCK

16 MHz < fMCK

≤ 20 MHz

64/fMCK

8 MHz < fMCK

≤ 16 MHz

52/fMCK

4 MHz < fMCK

≤ 8 MHz

32/fMCK

fMCK

≤ 4 MHz

20/fMCK

SCKp high-/low-level

width

tKH2,

tKL2

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

tKCY2/2 – 24

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

tKCY2/2 – 36

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

tKCY2/2 – 100

SIp setup time

(to SCKp

↑) Note 2

tSIK2

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V

1/fMCK + 40

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

1/fMCK + 40

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V

1/fMCK + 60

SIp hold time

(from SCKp

↑) Note 3

tKSI2

1/fMCK + 62

Delay time from SCKp

↓ to

SOp output Note 4

tKSO2

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2/fMCK +

240

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2/fMCK +

428

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

2/fMCK +

1146

Notes 1.

Transfer rate in the SNOOZE mode: MAX. 1 Mbps

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD

tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output

mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer

selected.

2. CSI01 and CSI11 cannot communicate at different potential.

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