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R5F10366ASP Datasheet(PDF) 50 Page - Renesas Technology Corp |
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R5F10366ASP Datasheet(HTML) 50 Page - Renesas Technology Corp |
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50 / 114 page  RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 50 of 109 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLr clock frequency fSCL 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 k Ω 400Note1 300Note1 kHz 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 k Ω 400Note1 300Note1 kHz 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 k Ω 300Note1 300Note1 kHz Hold time when SCLr = “L” tLOW 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 k Ω 1150 1550 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 k Ω 1150 1550 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 k Ω 1550 1550 ns Hold time when SCLr = “H” tHIGH 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 k Ω 675 610 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 k Ω 600 610 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 k Ω 610 610 ns Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 k Ω 1/fMCK + 190 Note3 1/fMCK + 190 Note3 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 k Ω 1/fMCK + 190 Note3 1/fMCK + 190 Note3 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 k Ω 1/fMCK + 190 Note3 1/fMCK + 190 Note3 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 k Ω 0 355 0 355 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 k Ω 0 355 0 355 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 k Ω 0 405 0 405 ns Notes 1. The value must be equal to or less than fMCK/4. 2. Use it with VDD ≥ Vb. 3. Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. IIC01 and IIC11 cannot communicate at different potential. (Remarks are listed on the next page.) |
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