R5F10366ASP datasheet(83/114 Pages) RENESAS

83 / 114 page

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 83 of 109

Transfer rate × 2 – {–Cb × Rb × ln (1 –

2.2

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 2.7 V

≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V

Maximum transfer rate =

[bps]

{–Cb × Rb × ln (1 –

2.0

Vb )} × 3

Transfer rate × 2 – {–Cb × Rb × ln (1 –

2.0

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.

The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

Maximum transfer rate =

[bps]

{–Cb × Rb × ln (1 –

1.5

Vb )} × 3

Transfer rate × 2 – {–Cb × Rb × ln (1 –

1.5

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.

Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for

the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).

For VIH and VIL, see the DC characteristics with TTL input buffer selected.

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