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R5F10366ASP Datasheet(PDF) 38 Page - Renesas Technology Corp

Part # R5F10366ASP
Description  True low-power platform (63 μA/MHz) for the general-purpose applications, with 1.8-V to 5.5-V operation, 2- to 16-Kbyte code flash memory, and 31 DMIPS at 24 MHz
PDF  114 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F10366ASP Datasheet(HTML) 38 Page - Renesas Technology Corp

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RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
R01DS0193EJ0250 Rev.2.50
Jan 17, 2025
Page 38 of 109
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
Transfer
rate Note4
Reception
4.0 V
≤ VDD ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V
fMCK/6
Note1
fMCK/6
Note1
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote3
4.0
1.3
Mbps
2.7 V
≤ VDD < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V
fMCK/6
Note1
fMCK/6
Note1
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote3
4.0
1.3
Mbps
1.8 V
≤ VDD < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
fMCK/6
Notes1, 2
fMCK/6
Notes1, 2
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote3
4.0
1.3
Mbps
Transmission
4.0 V
≤ VDD ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V
Note4
Note4
bps
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 1.4 k
Ω, Vb = 2.7 V
2.8
Note5
2.8
Note5
Mbps
2.7 V
≤ VDD < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Note6
Note6
bps
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 2.7 k
Ω, Vb = 2.3 V
1.2
Note7
1.2
Note7
Mbps
1.8 V
≤ VDD < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
Notes
2, 8
Notes
2, 8
bps
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 5.5 k
Ω, Vb = 1.6 V
0.43
Note9
0.43
Note9
Mbps
Notes 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
2.
Use it with VDD
≥ Vb.
3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V
≤ VDD ≤ 5.5 V)
16 MHz (2.4 V
≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V
≤ VDD ≤ 5.5 V)
4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V
≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate =
1
[bps]
{–Cb × Rb × ln (1 –
2.2
Vb )} × 3
1
Transfer rate × 2 – {–Cb × Rb × ln (1 –
2.2
Vb )}
Baud rate error (theoretical value) =
× 100 [%]
(
1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.



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