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R5F10366ASP Datasheet(PDF) 79 Page - Renesas Technology Corp

Part # R5F10366ASP
Description  True low-power platform (63 μA/MHz) for the general-purpose applications, with 1.8-V to 5.5-V operation, 2- to 16-Kbyte code flash memory, and 31 DMIPS at 24 MHz
PDF  114 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F10366ASP Datasheet(HTML) 79 Page - Renesas Technology Corp

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RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
R01DS0193EJ0250 Rev.2.50
Jan 17, 2025
Page 79 of 109
(3) During communication at same potential (simplified SPI (CSI) mode) (slave mode, SCKp... external clock
input)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
MAX.
SCKp cycle time Note 5
tKCY2
4.0 V
≤ VDD ≤ 5.5 V
20 MHz < fMCK
16/fMCK
ns
fMCK
≤ 20 MHz
12/fMCK
ns
2.7 V
≤ VDD ≤ 5.5 V
16 MHz < fMCK
16/fMCK
ns
fMCK
≤ 16 MHz
12/fMCK
ns
2.4 V
≤ VDD ≤ 5.5 V
12/fMCK
and 1000
ns
SCKp high-/low-level width
tKH2,
tKL2
4.0 V
≤ VDD ≤ 5.5 V
tKCY2/2–14
ns
2.7 V
≤ VDD ≤ 5.5 V
tKCY2/2–16
ns
2.4 V
≤ VDD ≤ 5.5 V
tKCY2/2–36
ns
SIp setup time (to SCKp
↑)
Note 1
tSIK2
2.7 V
≤ VDD ≤ 5.5 V
1/fMCK + 40
ns
2.4 V
≤ VDD ≤ 5.5 V
1/fMCK + 60
ns
SIp hold time
(from SCKp
↑) Note 2
tKSI2
1/fMCK + 62
ns
Delay time from SCKp
↓ to
SOp output Note 3
tKSO2
C = 30 pF Note 4
2.7 V
≤ VDD ≤ 5.5 V
2/fMCK + 66
ns
2.4 V
≤ VDD ≤ 5.5 V
2/fMCK + 113
ns
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp
↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp
↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp
↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
C is the load capacitance of the SOp output lines.
5.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps.
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Simplified SPI (CSI) mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User's device
SIp
SO



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