R5F10366ASP datasheet(82/114 Pages) RENESAS

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RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 82 of 109

(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

Unit

MIN.

MAX.

Transfer

rate Note4

Reception

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

fMCK/12

Note 1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLKNote 2

2.0

Mbps

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

fMCK/12

Note 1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLKNote 2

2.0

Mbps

2.4 V

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V

fMCK/12

Note 1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLKNote 2

2.0

Mbps

Transmission

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

Note 3

bps

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 1.4 k

Ω, Vb = 2.7 V

2.0

Note 4

Mbps

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Note 5

bps

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 2.7 k

Ω, Vb = 2.3 V

1.2

Note 6

Mbps

2.4 V

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V

Notes

2, 7

bps

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 5.5 k

Ω, Vb = 1.6 V

0.43

Note 8

Mbps

Notes 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode: 24 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 4.0 V

≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V

Maximum transfer rate =

[bps]

{–Cb × Rb × ln (1 –

2.2

Vb )} × 3

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